1. Field of the Invention
This invention pertains to a process for the formation of an integrated circuit structure, more particularly to the fabrication procedure associated with the manufacture of a single device memory cell incorporating field effect transistors (FET) a complete description of the type of device and a method of producing same is found in U.S. Pat. to Garnache et al. No. 3,841,926 issued Oct. 15, 1974. The invention especially relates to the profile of a doped oxide diffusion source in relation to the configuration of the actual diffusion and the control of parasitic capacitance.
As integrated circuit density has become greater and greater the problems of leakage currents and interference currents between adjacent integrated circuit devices has becomes more serious. Similarly the control of parasitic capacitance also becomes significant to maintain optimum operation of the device especially in FET memory arrays. It is to this latter aspect that the subject invention pertains.
Self alignment of various elements to fabricate semiconductor integrated circuits has been proposed and used for some time. The advantage of a self aligned structure is that the photolithographic alignment tolerances between certain critical levels on said circuit structures can be minimized thus obtaining a higher density of circuitry.
A problem which remains with present self aligned schemes is one of overlap parasitic capacitance caused by the very nature of the self aligned structure itself. This invention describes a method of fabricating a self aligning oxide diffusion structure which utilizes specific properties of the doped oxide diffusion source, the photolighography structure and the diffusion drive-in to fabricate a diffusion structure beneath the doped oxide source in a semiconductor body in which lateral extension of the edge of the diffusion can be tailored to reside out beyond the edge of the doped oxide pattern, entirely within the edges of said pattern or at points in between said limitations. The parasitic capacitance of this diffusion edge with other nearby structures can then be varied willfully, thus allowing it to become a circuit design parameter rather than a circuit design limitation.
Control of the overlap of the doped oxide source and the edge of the diffusion involves establishing the values of four independent parameters defined, explained and applied in this specification.
2. Description of the Prior Art
Prior teachings in the art relating to this invention pertain broadly to forming support layers on semiconductor wafers and removing portions of the semiconductor material so that separated semiconductor areas are exposed. Other disclosures are concerned with utilizing photoresist masks to form two or more individual patterns on semiconductor substrates with relatively high precision.
Likewise, the art is complete with teachings dealing with the formation of thermal oxides for masking purposes in the formation of active and passive integrated circuit elements. In bipolar technology high speed shallow junction transistor structures and processes are revealed wherein one or more low temperature oxide passivation layers are formed after the formation of a transistor base region and after the diffusion mask for the base region has been completely removed.
In general it can be said the art has taught the individual steps necessary to carrying out this invention but the sequence and control of a multiplicity of variables are new to the production of single device memory cells disclosed by this specification and the literature has not recognized the problem of parasitic capacitance resulting from the misalignment or overlap of the doped oxide or diffusion source where portions of this oxide remain on the substrate after diffusion into the substrate is complete.